Parasitic suppressing circuit

ABSTRACT

A circuit for suppressing parasitic oscillations across an inductor operating in a resonant mode is described. The circuit includes a switch means and resistive means connected serially across the inductor. A unidirectional resistive-capacitive network is also connected across the inductor and to the switch means to automatically render the switch means conducting when inductive current through the inductor ceases to flow.

United States Patent m Fowler et al.

[54] PARASITIC SUPPRESSING CIRCUIT [75] Inventors: John T. Fowler,Winthrop; Frank L.

Raposa, Concord, both of Mass.

21] Appl. No.: 253,405

[52] US. Cl. ..321/11, 317/DIG. 6, 321/45 C [51] Int. Cl.....,.., ..H02m1/18 [58] Field of Search ..'.....3l7/DIG. 6; 321/11,

[56] References Cited UNITED STATES PATENTS 1 June 5, 1973 ..3 l 7/DIG.6

3,189,796 6/1965 Tipton 3,560,820 2/1971 Unnewehr ..321/45 C 3,643,1292/1972 Marsh ..3l7/DIG. 6

Primary Examiner william M. Shoop, Jr.

Attorney-N. T. Musial, J. A. Mackinand John R. Manning [57] ABSTRACT 9Claims, 2 Drawing Figures 3,614,531 10/1971 oswald ..317/DlG.6

[ TIMING l CIRCUIT MoM l I I4 I 7 I5 I I l6 I l l L 1 v 1 PARASITICSUPPRESSING CIRCUIT ORIGIN OF THE INVENTION The invention describedherein was made by employees of the United States Government and may bemanufactured or used for governmental purposes by or for The Governmentof the United States of America, without the payment of any royaltiesthereon or therefor.

BACKGROUND OF THE INVENTION a switch. The switch is turned on and off ata predeter mined rate to supply current for one half cycle of operationto the inductor which resonates with the capacitor each time the switchopens. This provides alternating current output to the load. At the endof each resonant half cycle, parasitic oscillations may occur and maydamage or destroy solid state devices such as the switch which isusually a silicon controlled rectifier or the like.

In the past, parasitic oscillations have been damped by connecting aresistor and capacitor in series across the inductor which is generatingthe parasitic oscillations. Such a damping circuit has severaldisadvantages. First, the damping is always present across the inductorand will seriously degrade its Q. Additionally, in order to criticallydampthe parasitic oscillations, relatively low values of resistance andhigh values of capacitance must be used. This will result inunreasonably high power consumption and low efficiency for high powerinverter circuits.

OBJECTS AND SUMMARY OF THE INVENTION It is an object of the invention toprovide for the inductor of a resonant type inductor inverter, aparasitic oscillation suppressor which has substantially no effect onthe power inductor Q when current is being supplied to the inductor fromthe DC source and which has negligible effect on the inductor Q duringthe resonant half cycle when the current through the inductor iscollaps- It is another object of the invention to provide apparatus forcritically damping ringing oscillations which occur after the resonanthalf cycle of a power inductor a resonant inductor type DC to when theself-induced voltage across the inductor drops to approximately zero.

In summary, the invention provides for a resonant inductor, a parasiticoscillation suppressor circuit which causes substantially no degradationof the inductor 2, which requires no external control circuitry toactivate it and which is passive until the end of each resonant halfcycle.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic drawing ofcircuitry embodying the invention.

FIG. 2 is a graph at waveshapes which occur in a DC to AC inverter ofthe resonant inductor type.

DESCRIPTION OF A PREFERRED EMBODIMENT Referring now to FIG. 1, there isshown a resonant inductor type inverter 10 enclosed in dashed lines anda parasitic oscillation suppressor circuit 11 enclosed in dashed lines.The invertor 10 comprises an inductor 12 which has its upper end, asviewed in the figure, connected through a capacitor 13 to a cathodeelectrode 14c of a silicon controlled rectifier 14 which serves as aswitch means. An anode electrode 14a of the controlled rectifier 14 isconnected to the positive side of a DC power source 15. A negative sideof the power source 15 is connected via lead 16 to the lower end of theinductor 12, the lead 16 being grounded as at 17. The inductor 12 iscarried on a core 18 which may also carry a secondary winding 19 whichserves to couple electrical power from the inductor 12 to a load 20.

In order to provide voltage and current through the inductor 12 at apredetermined repetitive rate there is provided for the inverter 10 atiming circuit comprises electrical voltage pulses which transmitted toa gate electrode 14b of the controlled rectifier 14 via a lead 22 torender the controlled rectifier conducting. The timing pulses are ofshort duration. However, the controlled rectifier 14 continues toconduct after the end of the timing pulse until its current drops belowits holding value.

The parasitic oscillation suppressing circuit 11 comprises a dampingresistor 23 having its lower end con nected to an anode electrode 24a ofa controlled rectifier 24 which serves as a switch means for circuit 11.A cathode electrode 240 of the controlled rectifier 24 is connected bymeans of a lead 25 to the lower end of the inductor 12 thereby providinga complete current path. The upper end of the inductor 12 is connectedto an anode electrode of a diode 26 by means of a lead 27, the cathodeof diode 26 being connected to the upper end of the damping resistor 23which serves as a voltage dropping means.

Control circuitry for the switch means 24 is com prised of a diode 28, acapacitor 29, a resistor 30 and a diode 31 connected serially betweenthe leads 25 and 27 as-shown in FIG. 1. A point between the diode 28 andthe capacitor 29 is connected to a gate electrode 24b of the controlledrectifier 24 through a lead 32 to render the controlled rectifier 24conducting at the end of each resonant half cycle of the power inverter12 as will be explained presently. A time constant for the discharge ofcapacitor 29 is established by a resistor 33 connected in parallelrelationship to the serially connected diode 28 and capacitor 29.

To eliminate false triggering of the controlled rectifier 24, a resistor34 is connected between the gate electrode 24b and the lead 25. Theparasitic oscillation suppressing circuit 11 is completed by a capacitor35 connected between the anode electrode 24a and the cathode electrode24c of the controlled rectifier 24. The capacitor 35 suppresses voltagespikes which could possibly damage or destroy the controlled rectifier24.

Operation of the foregoing circuitry will not be described. Referring toFIG. 2A, there is depicted a trigger pulse 36 which is supplied at timet to the gate electrode 14b by the timing circuit 21 of FIG. 1. Thepulse 36 renders the controlled rectifier 14 conducting causing avoltage pulse as illustrated at 37 in FIG. 2B

to appear at the upper end of the inductor 12 with respect to ground 17.When the capacitor 13 becomes fully charged, the voltage across theinductor 12 reverses producing a voltage pulse as shown at 38 in FIG.28. At the end of the inductive half cycle which produced voltage pulse38, spurious oscillations as shown at 39 will be produced because of therapid turn off of inductor 12. These oscillations, as indicatedpreviously, can destroy solid state components such as the siliconcontrolled rectifier 14. The current through the inductor during theexistence of pulses 37 and 38 is shown at 40 in FIG. 2C. Currentoscillations 41 correspond to the parasitic voltage oscillations 39 ofFIG. 2B.

The desired voltage waveshape for inductor 12 is shown in FIG. 2D andcomprises the voltage pulse 37 produced by current supplied to theinductor while the controlled rectifier 14 is conducting during t, to tand the voltage pulse 39 which occurs during the inductive half cycle tto l As shown at 42, the voltage across the inductor 12 is permitted tobecome only slightly positive at the end of the voltage pulse 39 anddoes not again become negative during the cycle of operation which endsat 2 During the inductive cycle, the lower end of the inductor l2ispositive with respect to its upper end as shown by the voltage pulse39 of FIG. 2. Consequently, current flows from the lower end of theinductor 12 through the diode 28 to the lower side of capacitor 29.

Current flows from the upper side of capacitor 29 through the resistor30, the diode 31 and the lead 27 to the upper negative end of inductor12. I

At t the end of the inductive cycle, the voltage across the inductor 12decreases very rapidly towards as indicated at 43 in FIG. 2D. Capacitor29 immediately discharges into the gate electrode 248 of the controlledrectifier 24 rendering the latter conducting. At this time the upper endof the inductor 12 is beginning to become positive but, because of theconduction of controlled rectifier 24 which effectively connects thedamping resistor 23 across inductor 12, only a small positive voltageappears across the inductor as indicated at 42 in FIG. 2D. Thus, theparasitic oscillation which would normally appear across the inductor 12at the end of the inductive half cycle are critically damped when thedamping resistor 23 is connected across the inductor 12 by theconduction of the controlled rectifier 24.

From the foregoing it will be seen that, during the conduction of thecontrolled rectifier 14, in accordance with the invention, a parasiticoscillation suppression circuit 11 draws no power from the inductor 12other than a slight current due to the presence of a protectivecapacitor 35. After the controlled rectifier 14 turns off to begin theinductive half cycle, the only power drawn from the inductor 12 is thatresulting by the current required to charge the capacitor 29 of theparasitic oscillation suppression circuit 11. Advantageously, thedamping resistor 23 absorbs power from the inductor 12 only when it isdesired that parasitic oscillation be critically damped and itsinsertion in the circuit is accomplished automatically without any ex-.ternal timing circuits.

It will be understood that changes and modifications may be made to theabove described circuitry by those skilled in the art without departingfrom the spirit and scope of the invention as set forth in the claimsappended hereto.

What is claimed is:

1. A parasitic oscillation suppressor for use with a power inductor of aresonant type inverter, said suppressor comprising:

switch means having power electrodes and a control electrode; firstvoltage dropping means connected serially with said power electrodes ofsaid switch across said power inductor;

second and third voltage dropping means connected serially between oneend of said power inductor and the other end of same;

first unidirectional conducting means and first energy storage meansconnected serially in the order mentioned between said one end of saidpower inductor and a point intermediate said second and third voltagedropping means; and

means connecting a point intermediate said first unidirectionalconducting means and said first energy storage means to said controlelectrode of said switch means.

2. The circuit of claim 1 wherein said first, second and third voltagedropping means are resistors.

3. The circuit of claim 1 and including a second unidirectionalconducting means connected between said third voltage dropping means andsaid other end of said power inductor and poled to pass current in thesame direction as said first unidirectional conducting means.

4. The circuit of claim 3 wherein said switch means is a solid-statecontrolled rectifier having anode, cathode and gate electrodes.

5. The circuit of claim 4 and including second energy storage meansconnected between said anode and said cathode of said controlledrectifier, and third unidirectional conducting means connected in serieswith said first voltage dropping means between said second energystorage means and said other end of said inductor, said thirdunidirectional conducting means being poled to pass current in the samedirection as said SCR.

6. The circuit of claim 5 and including fourth voltage dropping meansconnected between said gate electrode and said one end of said powerinductor.

'7. The circuit of claim 5 wherein said first and second energy storagemeans are capacitorsv 8. The circuit of claim 5 wherein saidfirst andsecond unidirectional conducting means are solid-state diodes.

9. A parasitic oscillation suppressor for use with a power inductor of aresonant type inverter, said suppressor comprising switch means havingpower electrodes and a control electrode; first voltage dropping meansconnected serially with saidpower electrodes of said switch across saidpower inductor;

a first capacitor connected to said control electrode of said switchmeans;

means for charging said capacitor during the inductive half cycle of thepower inductor; and

means for limiting the discharge rate of said capacitor whereby thedischarge time of said capacitor is of adequate duration to render saidswitch means conducting.

1. A parasitic oscillation suppressor for use with a power inductor of aresonant type inverter, said suppressor comprising: switch means havingpower electrodes and a control electrode; first voltage dropping meansconnected seriallY with said power electrodes of said switch across saidpower inductor; second and third voltage dropping means connectedserially between one end of said power inductor and the other end ofsame; first unidirectional conducting means and first energy storagemeans connected serially in the order mentioned between said one end ofsaid power inductor and a point intermediate said second and thirdvoltage dropping means; and means connecting a point intermediate saidfirst unidirectional conducting means and said first energy storagemeans to said control electrode of said switch means.
 2. The circuit ofclaim 1 wherein said first, second and third voltage dropping means areresistors.
 3. The circuit of claim 1 and including a secondunidirectional conducting means connected between said third voltagedropping means and said other end of said power inductor and poled topass current in the same direction as said first unidirectionalconducting means.
 4. The circuit of claim 3 wherein said switch means isa solid-state controlled rectifier having anode, cathode and gateelectrodes.
 5. The circuit of claim 4 and including second energystorage means connected between said anode and said cathode of saidcontrolled rectifier, and third unidirectional conducting meansconnected in series with said first voltage dropping means between saidsecond energy storage means and said other end of said inductor, saidthird unidirectional conducting means being poled to pass current in thesame direction as said SCR.
 6. The circuit of claim 5 and includingfourth voltage dropping means connected between said gate electrode andsaid one end of said power inductor.
 7. The circuit of claim 5 whereinsaid first and second energy storage means are capacitors.
 8. Thecircuit of claim 5 wherein said first and second unidirectionalconducting means are solid-state diodes.
 9. A parasitic oscillationsuppressor for use with a power inductor of a resonant type inverter,said suppressor comprising switch means having power electrodes and acontrol electrode; first voltage dropping means connected serially withsaid power electrodes of said switch across said power inductor; a firstcapacitor connected to said control electrode of said switch means;means for charging said capacitor during the inductive half cycle of thepower inductor; and means for limiting the discharge rate of saidcapacitor whereby the discharge time of said capacitor is of adequateduration to render said switch means conducting.